1. Field of the Invention
The present invention generally relates to fuse structures used in semiconductor technology for implementation of redundancy or custom wiring and, more particularly, to fuse structures having vertical fuse link sidewalls to promote reliable and reproducible laser cutting processes.
2. Background Description
Redundancy in integrated circuit memories is part of current chip manufacturing strategy to improve yield. By replacing defective cells with redundant circuits on chips, integrated circuit memory yields are significantly increased. The practice is to cut or blow conductive connects (fuses) which allow redundant memory cells to be used in place of nonfunctional cells. In the manufacture of integrated circuits, it is also common practice to provide for customization of chips and modules to adapt chips to specific applications. In this way, a single integrated circuit design may be economically manufactured and adapted to a variety of custom uses.
Typically, fuses or fusible links are incorporated in the integrated circuit design, and these fuses or fusible links are selectively blown, for example, by passing an electrical current of sufficient magnitude through them to cause them to open. For example, U.S. Pat. No. 3,959,047 to Alberts et al. discloses a metal fuse construction in the form of straight links which are "necked" to cause a high current concentration to heat and open the links. An on-chip programmable polysilicon fuse is described in IBM Technical Disclosure Bulletin, vol. 29, no. 3, August 1986, pp. 1291, 1292, and a tungsten/aluminum fuse blown by electromigration is described in IBM Technical Disclosure Bulletin, vol. 31, no. 5, October 1988, pp. 347, 348.
An alternative to blowing fuse links with a programmable high current is to use a laser to blow the fuses. For modern multi-level metallization integrated circuits (ICs), the opening of fuse windows with fuse links lying very close to the substrate (e.g., bit-line or Word-line) is of concern. The dielectric thickness on top of fuses suffers from non-uniformities caused by deposition, planarization and etch processes. As a result, a designer tries to raise the fuses to an upper metallization level to reduce the dielectric fuse etch distance. Usually, upper metallizations are patterned by reactive ion etch (RIE) which exhibits in many cases a microloading effect. Specifically, features created with small spacings possess vertical sidewalls while features with large spacings (such as fuses) have sloped sidewalls. This sidewall inclination, however, degrades the fuse deletion process via laser ablation since a significant portion of the laser energy is reflected by the sloped fuse sidewalls. In addition, the variation of the slope angle leads to varied laser absorption within the fuse resulting in an unstable fuse cut process.
Alternatively, metallization can be patterned by damascene process in which grooves with a certain pattern are first formed within a dielectric film. Thereafter, the metal is deposited and subsequently removed from the top of the dielectric film, using for example a chemical-mechanical polish. As a result, the metal remains only in the patterned grooves. However, for a low density of metal such as the fuse area, the removal of metal on top of the dielectric film might result in a reduction of metal stack height due to dishing and erosion. This, in turn, results in a variation in fuse height resulting in a lack of reliability of the fuse cutting process by laser.